The present invention relates to a method of driving a passive matrix-addressable display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis.
Passive matrix addressing implies the use of two sets of parallel electrodes that cross each other, typically in orthogonal fashion, creating a matrix of crossing points that can be individually accessed electrically by selective excitation of the appropriate electrodes from the edge of the matrix. Advantages of this arrangement include simplicity of manufacture and high density of crossing points, provided the functionality of the matrix device can be achieved via the two-terminal connections available at each crossing point. Of particular interest in the present context are display and memory applications involving matrices where the electrodes at each crossing point sandwich a material in a capacitor-like structure, henceforth termed a xe2x80x9ccellxe2x80x9d, and where the material in the cells exhibits polarizability and hysteresis. The latter property confers non-volatility on the devices, i.e. they exhibit a memory effect in the absence of an applied external field. By application of a potential difference between the two electrodes in a given cell, the material in the cell is subjected to an electric field which evokes a polarization response, the direction and magnitude of which may be thus set and left in a desired state, representing e.g. a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in a memory application or a brightness level in a display application. Likewise, the polarization status in a given cell may be altered or deduced by renewed application of voltages to the two electrodes addressing that cell.
Examples of passive matrix devices employing ferroelectric memory substances can be found in the literature dating back 40-50 years. Thus, E. G. Merz and J. R. Anderson described a barium titanate based memory device in 1955 (W. J. Merz and J. R. Anderson, xe2x80x9cFerroelectric storage devicesxe2x80x9d, Bell.Lab.Record. 1, pp. 335-342 (1955)), and similar work was also reported by others promptly thereafter (see, e.g. C. F. Pulvari xe2x80x9cFerroelectrics and their memory applicationsxe2x80x9d, IRE Transactions CP-3, pp. 3-11 (1956), and D. S. Campbell xe2x80x9cBarium titanate and its use as a memory storexe2x80x9d, J. Brit. IRE 17 (7) pp. 385-395 (1957)). An example of a passive matrix addressed display rendered non-volatile by a ferroelectric material can be found in U.S. Pat. No. 3,725,899 (W. Greubel) filed in 1970.
In view of its long history and apparent advantages, it is remarkable that the passive matrix addressing principle in conjunction with ferroelectrics has not had a greater impact technologically and commercially. While important reasons for this may be traced back to the lack of ferroelectric materials that satisfy the full range (technical and commercial) of minimum requirements for the devices in question, a major factor has been certain inherent negative attributes of passive matrix addressing. Prominent among these is the problem of disturbing non-addressed crossing points. The phenomenon is well recognized and extensively discussed in the literature, both for displays and in memory arrays. Thus, the basics shall not be discussed here, but the reader is referred to, e.g.: A. Sobel: xe2x80x9cSome constraints on the operation of matrix displaysxe2x80x9d, IEEE Trans.Electron Devices (Corresp.) ED-18, p. 797 (1971), and L. E. Tannas Jr., xe2x80x9cFlat panel displays and CRTsxe2x80x9d, pp. 106 and seq., (Van Nostrand 1985). Depending on the type of device in question, different criteria for avoiding or reducing disturbance of non-addressed crossing points can be defined. Generally, it is sought to lower the sensitivity of each cell in the matrix to small-signal disturbances, which can be achieved by cells that exhibit a non-linear voltage-current response, involving e.g. thresholding, rectification and/or various forms of hysteresis.
Although general applicability is claimed for the present invention, particular focus shall be directed towards ferroelectric memories, where a thin film of ferroelectric material is stimulated at the matrix crossing points, exhibiting a hysteresis curve as illustrated generically in FIG. 1. Typically, writing of a bit is accomplished by applying a voltage differential across the film at a crossing point, causing the ferroelectric to polarize or switch polarization. Reading is analogously achieved by applying a voltage of a given polarization, which either causes the polarization to remain unchanged after removal of the voltage or to flip to the opposite direction. In the former case, a small current will flow in response to the applied voltage, while in the latter case the polarization change causes a current pulse of magnitude larger than a predefined threshold level. A crossing point may arbitrarily be defined as representing a xe2x80x9c0xe2x80x9d bit in the former case, a xe2x80x9c1xe2x80x9d bit in the latter.
A material with hysteresis curve as shown in FIG. 1 will change its net polarization direction upon application of a field that exceeds VC. However, partial switching shall take place upon application of voltages below this value, to an extent depending on the material in question. Thus, in a matrix with a large number of crossing points, repeated stimuli of non-addressed crossing points may ultimately degrade the polarization states in the matrix to the point where erroneous reading results. The amount and type of stimulus received by non-addressed crossing points in a cross-bar passive matrix during write and read operations depends on how the voltages are managed on all addressing lines in the matrix during these operations, henceforth termed the xe2x80x9cpulsing protocolxe2x80x9d. The choice of voltage pulsing protocol depends on a number of factors, and different schemes have been proposed in the literature, for applications involving memory materials exhibiting hysteresis. Examples of prior art shall now be given.
U.S. Pat. No. 2,942,239 (J. P. Eckert, Jr. and al.) discloses pulsing protocols for memory arrays with magnetic cores, each with a magnetic hysteresis curve analogous to the ferroelectric one shown in FIG. 1. Although claiming general applicability for memory elements exhibiting bistable states of remnant polarization, including ferroelectrics, their invention contains only specific teachings on magnetic data storage where separate contributions to the total magnetic flux in each cell are added or subtracted from several independent lines intersecting in each cell. This is reflected in how cells are linked up in the proffered embodiments, with a readout protocol providing superposition of a slow, or xe2x80x9cbackgroundxe2x80x9d biasing stimulus being applied to all or a subset (e.g. a column or a row) of the cells in the matrix, and with a fast selection pulse being applied between the crossing lines containing the addressed cell. No teachings are given on efficient voltage protocols for two-terminal, capacitor-like memory cells combining high speed, random access to data with restoration of the destructively read information.
U.S. Pat. No. 3,002,182 (J. R. Anderson) concerns the problem of polarization loss by partial switching of ferroelectric memory cells in passive matrix addressed arrays of ferroelectric-filled capacitors. To reduce the partial switching polarization loss during writing, this patent teaches the use of simultaneous application of addressing pulses to an addressed row and column such that the former executes an electrical potential swing of typically +2Vs/3 to +3Vs/4 (where Vs is the nominal switching voltage) while the latter swings to a negative value sufficient for the potential difference between the electrodes at the selected crossing point to reach the value Vs. With the remaining columns being switched to a potential in the range +Vs/3 to +Vs/4, only the selected cell in the matrix is subjected to a significant switching field, and partial switching at the other crossing points is strongly reduced (the reduction depends on the material properties of the ferroelectric, in particular the shape of the hysteresis curve and the magnitude of the dielectric constant). In an alternative pulsing scheme, the same patent teaches the application of additional xe2x80x9cdisturbance compensating pulsesxe2x80x9d subsequent to each writing operation, where the selected row is clamped at zero potential while the selected and non-selected columns are pulsed to +Vs/4 to +Vs/3 and xe2x88x92Vs/4 to xe2x88x92Vs/3, respectively. The latter operation is claimed to reduce the partial switching induced loss of polarization even further. No physical explanation was provided for this choice of pulsing scheme, however, which appears to rely to a large degree on the inventor""s empirical experience with the ferroelectric materials of his day, in particular barium titanate. While the basic choice of polarities appear plausible, the description given is insufficient to provide an adequate guide to selection of pulse magnitudes and timing in concrete terms for generalized cases. For reading out the stored information or clearing the cells before a writing operation, the inventor proposes the application of the full switching voltage xe2x88x92Vs to the selected row or rows, referring to xe2x80x9ca manner well known in the artxe2x80x9d. Selection of the column electrode voltages is treated in a nebulous fashion. It may appear that the selected column electrode is clamped at ground, with all non-selected column electrodes biased to xe2x88x92Vs/3 or xe2x88x92Vs/4 (cf. FIG. 4B in U.S. Pat. No. 3,002,182). However, this leads to a voltage load of 2Vs/3 to 3Vs/4 on the non-selected cells in the same row as the selected cell, with obvious danger of partial switching. Thus, it would at best seem that the invention shall be poorly suited for situations where a large number of read operations are involved between each write, and the general applicability to realistic ferroelectric devices appears doubtful.
U.S. Pat. No. 3,859,642 (J. Mar) discloses a memory concept based on a passive matrix addressing scheme, where an array of capacitors with programmable bistable capacitance values is subjected to a two-level excitation during the reading cycle. The memory function resides in the bistability of the capacitors, which are assumed to be of the metal-insulator-semiconductor (MIS) type or equivalent, exhibiting a hysteresis loop which is centered around an offset voltage and well removed from the zero offset point. Writing of data is achieved by biasing the row and column lines crossing at the selected capacitor to polarities +V and xe2x88x92V, respectively, alternatively to xe2x88x92V and +V, respectively, depending on which of the two bistable states is to be written. The resulting net bias is thus +xe2x88x922V on the selected capacitor, and does not exceed an absolute magnitude V on non-selected capacitors, where V is defined as being below threshold for writing. Partial writing is apparently not considered to be a problem, and no particular provisions are described in that connection beyond the simple scheme referred here. Thus, the teachings of U.S. Pat. No. 3,859,642 cannot be seen as having any prior art significance relative to the subject matter of the present invention.
A one-third voltage selection scheme for addressing a ferroelectric matrix arrangement is disclosed in U.S. Pat. No. 4,169,258 (L. E. Tannas, Jr.). In this case, the x- and y lines in a passive matrix addressing arrangement are subjected to a pulsing protocol where (unipolar) voltages with relative magnitudes 0, ⅓, ⅔ and 1 are applied in a coordinated fashion to all x and y lines. Here, voltage value 1 is the nominal voltage amplitude employed for driving a given cell from a logic state xe2x80x9cOFFxe2x80x9d to xe2x80x9cONxe2x80x9d, or vice versa, with the typical coercive voltage being exemplified as a value between xc2xd and ⅔. An important limitation of the scheme taught in the patent is that the pulse protocols are predicated upon all cells starting out with the same initial polarization magnitude and direction (xe2x80x9cOFFxe2x80x9d), i.e. the whole matrix must be blanked to an xe2x80x9cOFFxe2x80x9d state before a new pattern of states can be written into the matrix cells. Furthermore, any xe2x80x9cONxe2x80x9d state on the same y-line as the addressed cell shall receive a disturb pulse of magnitude ⅔ in the direction of the xe2x80x9cOFFxe2x80x9d state, leading to partial switching in most known ferroelectrics. While these limitations may be acceptable in certain types of displays and memories, this is not the case in the vast majority of applications.
Total blanking is not subsumed under what Tannas Jr. terms the conventional method xe2x80x9cone-half selection schemexe2x80x9d, which is described in detail in the cited U.S. Pat. No. 4,169,258. However, the latter scheme exposes the non-selected cells to disturbing pulses of relative value xc2xd. This is generally deemed unacceptable for all practical memory applications employing traditional ferroelectric materials such as inorganic ceramics. Furthermore, the one-half voltage selection scheme is only described in terms of single switching events in the addressed cells, which destroy the pre-switching polarization states.
Thus, in passive matrix-addressable memory and display applications where it is desired to be able to change the logic content of individual cells without disturbing other cells or having to blank and reset the whole device, there is a clear need for improvement over the existing prior art.
The present invention can provide voltage vs. time protocols for driving the x and y passive matrix addressing lines in non-volatile memories exhibiting ferroelectric-like hysteresis curves so as to minimize disturbance of non-selected memory cells during writing as well as reading of data to/from said memories.
The present invention can describe voltage protocols that reduce charging/discharging transients and thus achieve high speed.
In an embodiment of the present invention the polarizable material can be a ferroelectric material, wherein the polarization state of individual, separately selectable cells can be switched to a desired condition by application of electric potentials or voltages to word and bit lines forming an addressing matrix, wherein a voltage pulsing protocol with n voltage or potential levels, nxe2x89xa73, such that the voltage pulsing protocol defines a timing sequence for individually controlling the voltage levels applied to word and bit lines forming the matrix in a time-coordinated fashion, arranging said timing sequence to encompass at least two distinct parts, including a xe2x80x9cread cyclexe2x80x9d during which charges flowing between said selected bit line(s) and the cells connecting to said bit line(s) are sensed, and a xe2x80x9crefresh/write cyclexe2x80x9d during which polarization state(s) in cells connecting with selected word and bit lines are brought to correspond with a set of predetermined logical states or data values.
The present invention further addresses pulsing protocols for the addressing of individual crossing points in passive matrices used for data storage and display purposes. The present invention addresses the avoidance of disturbing non-addressed crossing points in the same matrices and further addresses minimizing the cumulative signal from non-addressed cells in such matrices during reading of stored data. Applications shall typically involve, but are not limited to, matrices containing a ferroelectric thin film that acts as non-volatile memory material.
A further embodiment of the present invention describes voltage protocols that permit simple, reliable and cheap electronic circuitry to perform drive and sense operations on the memory matrices.
The features of the present invention can be achieved with a method, which controls individually a potential on selected word and bit lines to approach or coincide with one of n predefined potential levels, where nxe2x89xa73. The potentials on said selected word and bit lines form subsets of n potentials involving nWORD and nBIT potentials, respectively. Additionally, the potentials are controlled on all word-and bit lines in a time-coordinated fashion according to a protocol or timing sequence, whereby word lines are latched in a predetermined sequence to potentials are controlled selected among the nWORD potentials. Bit lines are either latched in a predetermined sequence to potentials selected among the nBIT potentials or they are latched during a certain period of the timing sequence connected to circuitry that senses the charges flowing between the bit line(s) and the cells connecting to said bit line(s). The timing sequence is arranged to encompass at least two distinct parts, including a xe2x80x9cread cyclexe2x80x9d where charges flowing between said selected bit line(s) and the cells connecting to said bit line(s) are sensed, and a xe2x80x9crefresh/write cyclexe2x80x9d where polarization state(s) in cells connecting with selected word-and bit lines are brought to correspond with a set of predetermined values.
According to an embodiment of the invention, one or more bit lines float in response to charges flowing between a bit line and the cells connecting to the bit line during the read cycle, and latching all voltages on the word and bit lines during the refresh/write cycle.
In a further embodiment of the present invention the values n=3, nWORD=3, and nBIT=3 are selected in case voltages across non-addressed cells that do not significantly exceed VS/2, where VS is the voltage across the addressed cell during read, refresh and write cycles.
In another embodiment of the present invention the values n=4, nWORD=4, and nBIT=4 are selected in case voltages across non-addressed cells that do not significantly exceed VS/3, where VS is the voltage across the addressed cell during read, refresh and write cycles.
In still another embodiment of the present invention the values n=5, nWORD=3, and nBIT=3 are selected in case voltages across non-addressed cells that do not significantly exceed VS/3, where VS is the voltage across the addressed cell during read, refresh and write cycles.
The present invention can subject non-addressed cells along an active word line and along active bit line(s) to a maximum voltage during the read/write cycle that deviates by a controlled value from the exact values VS/2 or VS/3. The non-addressed cells can be subjected along an active word line to a voltage of a magnitude that exceeds the exact values VS/2 or VS/3 by a controlled voltage increment, while at the same time subjecting non-addressed cells along selected active bit lines to a voltage of a magnitude that is less than the exact values VS/2 or VS/3 by a controlled voltage decrement. The controlled voltage increment and voltage decrement can be equal to each other.
The present invention can add a controlled voltage increment xcex41 to potentials "PHgr"inactiveWL of inactive word lines and adding a controlled voltage increment xcex42 to potentials "PHgr"inactiveBL of inactive bit lines, where xcex41=xcex42=0 corresponds to the voltage pulsing protocols with maximum VS/2 or VS/3 voltage exposure on non-selected cells. In this connection is preferably xcex41=xcex42xe2x89xa00.
The present invention can control a quiescent potential (the potential imposed on the word and bit lines during the time between each time the voltage pulsing protocol is employed) to have the same value on all word and bit lines, i.e. a zero voltage is imposed on all cells. Further the present invention can select the quiescent potentials on one or more of the word and bit lines among one of the following: a) System ground, b) Addressed word line at initiation of pulsing protocol, c) Addressed bit line at initiation of pulsing protocol, d) Power supply voltage(VCC). Additionally, the present invention can select the potential on a selected bit line or bit lines in a quiescent state such that it differs from that at the onset of a floating period (read cycle), and bringing said potential from a quiescent value to that at the onset of the floating period, where it is latched for a period of time comparable to or exceeding a time constant for charging the bit line (xe2x80x9cpre-charge pulsexe2x80x9d). The present invention can precede the read cycle with a voltage shift on inactive word lines, whereby the non-addressed cells on an active bit line are subjected to a voltage bias equal to that occurring due to the active bit line voltage shift during the read cycle. The voltage shift on the inactive word lines starting at a selected time preceding said the voltage shift on the active bit line, and terminate at the time when the latter voltage shift is initiated, in such a way that a perceived voltage bias on said non-addressed cells on the active bit line is continuously applied from the time of initiation of the voltage shift on the inactive word lines, up to the time of termination of said voltage shift on the active bit line (xe2x80x9cpre-charge pulsexe2x80x9d).
Additionally, the present invention can apply a pre-read reference cycle which precedes the read cycle and is separated from it by a selected time, and which mimics precisely the voltage pulsing protocol and current detection of said read cycle. The exception being that no voltage shift is imposed on an active word line during the pre-read reference cycle. The present invention can employ a signal recorded during the pre-read reference cycle as input data to the circuitry that determines the logic state or a data value of the addressed cell, in which case the signal recorded during the pre-read reference cycle may be subtracted from a signal recording during the read cycle.